1. Technical Field
This disclosure is directed to integrated circuits, and more particularly, to networks for distributing a clock signal in an integrated circuit.
2. Description of the Related Art
Modern digital integrated circuits use clock signals to synchronize the operation of sequential circuits implemented therein. A given clock signal may be provided to a number of circuits (e.g., flip-flops) within a corresponding clock domain. Since the number of circuits utilizing the clock signal may be large and relatively remote from the clock source, a clock distribution network (sometimes referred to as a ‘clock tree’) may be used to distribute the clock signal. A clock tree may include a number of levels, with buffers implemented at the various levels. At a node known as a root node of the clock tree, the clock signal may be received by a buffer from a clock source. The buffer may distribute the clock signal to additional buffers of the next level of the clock tree. At each level, an expanding number of buffers (with respect to a previous level) may distribute the clock signal. At the output of each buffer of a final level, the clock signal may be distributed to the various circuits that use it for synchronization (also known as ‘clock consumers). Nodes at which the clock signal is received for distribution directly to the clock consumers are referred to as leaf nodes.
In distributing a clock signal, it is important that its integrity be maintained. Jitter, an undesired deviation from true periodicity, is one factor that can adversely affect a clock signal. If left unchecked, jitter can cause erroneous operation of synchronous circuits and may even cause them to fail. Causes of jitter can include such factors as power supply noise, intrinsic device noise in the clock generator, and crosstalk with wires carrying other signals. Although it cannot be completely eliminated, it is possible to design circuits to tolerate a certain amount of jitter.